The present invention is generally related to semiconductor devices and, more particularly, to the design of metal contacts and interconnections for semiconductor integrated circuits to eliminate electromigration failure. The invention also relates to providing various processes for obtaining the designed structure.
The reliability of aluminum-based interconnections in microelectronic circuits is generally limited by a phenomenon known as electromigration. As microelectronic circuits are made more dense in order to improve performance, the electric fields (and resulting current densities) in the aluminum interconnects increase. Hence, as circuit densities increase, the rate of electromigration also increases.
Electromigration leads to circuit failure primarily via two mechanisms. In the first, aluminum electromigrates away from a region in the interconnect faster than the availability of additional atoms can take its place. This process generates a void in the interconnection. Growth of this void increases the electrical resistance of the interconnection to a point where circuit failure occurs. The second means by which electromigration failure occurs is when metal electromigrates into a region faster than it escapes the region, thus locally piling up metal atoms (called extrusions) to a point where it extends to the adjacent interconnection line, thereby causing an electrical short circuit.
The problem of electromigration has been approached in a number of ways, the two most common are: (1) introducing a second species into the parent metal, e.g., alloying aluminum with a 0.2% to 4% copper, and (2) utilizing a redundant metal layer, e.g., titanium, tungsten or chromium layer(s) under and/or over the aluminum lines.
The addition of Cu into the Al line has been described by Ames, et al., in U.S. Pat. No. 3,879,840, and of common assignee. The formation of a thin intermetallic layer within the Al-Cu has been described by J. K. Howard in U.S. Pat. Nos. 4,017,890 and 4,154,874, and of common assignee. While the above methods increase electromigration lifetime, it has been found that electromigration failure cannot be totally avoided because void growth cannot completely be suppressed, i.e., void sizes increase with time. The use of redundant layers can extend the electromigration lifetime of metal lines by a factor of 10 to 100 over non-redundant schemes. The present invention, however, offers a lifetime extension in excess of 1000X. This is because with the present invention, void growth is totally eliminated, which is made possible by a phenomenon known as the short-length effect.
The short-length effect takes place in short aluminum interconnections if an electrical current is supplied through leads of materials in which aluminum diffusivity is low. The physical origin of the short-length effect is the build-up of backstress as aluminum atoms pile up against the diffusion barrier leads; this backstress counteracts the electromigration driving force. A steady-state condition arises in situations where the backstress exactly balances the electromigration driving force. Under this condition, no further electromigration damage results.
The existence of the short-length effect has been demonstrated by several investigators as, for instance, by H. V. Schreiber in the article: xe2x80x9cElectromigration Threshold of Aluminum Filmsxe2x80x9d published in Solid State Electronics, Vol. 28, No. 6, p. 617, by R. G. Filippi, et al., in the article: xe2x80x9cEvidence of the Electromigration Short-Length Effect in Aluminum based Metallurgy with Tungsten Diffusion Barriersxe2x80x9d published in the Proceedings of the Materials Research Symposium, Vol. 309, pp. 141-148, and by X. X. Li et al., in the article: xe2x80x9cIncrease in Electromigration Resistance by Enhancing Backflow Effectxe2x80x9d published in the Proceedings of the 30th International Reliability Physics Symposium, March 1992, p. 211. Based on experimental evidence, an interconnection of length L will show electromigration immunity for an applied current density below a critical value jcr. This jcr has been found to be inversely proportional to the interconnection length L. The above investigators of the short-length effect use various schemes to prove the existence of this phenomenon. However, these schemes do not utilize the self-aligned features and fine pitch which are essential for the manufacturability of Very Large and for Ultra Large Scale Integration circuits (VLSI and ULSI).
Accordingly, it is an object of the present invention to describe several metallurgical structures that utilize the short-length phenomenon practiced in a VLSI and ULSI circuit environment.
It is another object of the present invention to provide an interconnection metallurgy having ultra small pitch and which is immune to electromigration failure.
It is a further object of the present invent-ion to form an aluminum or copper metallurgy line having diffusion barrier interposed in series every 50 to 100 xcexcm.
It is still another object of the present invention to form an interconnection line by interspersing islands of refractory metal between sections of a high conductivity material.
It is yet another object of the present invention to provide an underlayer, an overlayer or both, contacting the individual sections of high conductivity and sections of refractory metal to ensure better electrical integrity.
It is still a more particular object of the present invention to provide studs linking interconnection lines between different levels of an IC chip having the same structure as that described for the interconnection line.
The invention provides several distinct embodiments, each having a self-alignment feature, to achieve the desired metallurgical structure. In some aspects of the present invention, an aluminum segment is defined by an additive process, e.g., lift-off or Damascene, whereas a tungsten segment is defined by either an additive or a subtractive process. In some other aspects of the invention, the aluminum segment is defined only by a subtractive process, e.g., Reactive-Ion-Etch (RIE), whereas the tungsten segment is defined by either an additive or a subtractive process.
In accordance with one embodiment of the present invention, there is provided an interconnection wiring structure on an insulated substrate in an integrated circuit chip for minimizing electromigration, that includes: a sublayer of a diffusion barrier metal on the insulated layer; sections of high conductivity metal on the sublayer; coplanar sections of the diffusion barrier metal interspersed between the sections of high conductivity metal, such that the sections of high conductivity metal and the sections of diffusion barrier metal contact each other to carry an electrical current, such that the electrical current sequentially crosses the sections of high conductivity metal and the sections of diffusion barrier metal.
In another aspect of the invention, there is provided in an integrated circuit chip having more than one level of wiring, each of the levels of wiring having at least one stud linking at least one interconnection in a first level to another interconnection in a second level, the interconnections designed for minimizing electromigration, the stud including: sections of conductive material; sections of diffusion barrier metal interspersed with the conductive sections, the sections of conductive material and the sections of diffusion barrier metal contacting each other to provide electrical continuity, such that an electrical current flowing through the stud sequentially crosses each of the conductive sections and the diffusion barrier metal sections.